Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
نویسندگان
چکیده
منابع مشابه
Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-c...
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ژورنال
عنوان ژورنال: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
سال: 2013
ISSN: 0916-8508,1745-1337
DOI: 10.1587/transfun.e96.a.1579